Subject : Re: 8051 and DRAM From : Scott May > I saw once an article on the use of DRAM with the 8051, but can't > remember where. Could someone give me a pointer on that subject? Look at the application note, AN417, available in the 8051 applications book, and I think on the Philips web site as well. It's a printer buffer, using DRAM for storage, and might be a good start. Re: Joao Paulo Sousa and 8051 with DRAM Hi Joao, Try AN417, 256k Centronics printer buffer using the 87C451 microcontroller, in the IC20 8-Bit Microcontrollers Data Handbook. Also, may be on the Philips web page if you have internet access. Ap note describes how to connect 256k DRAM chips to the 87C451 (enhanced 8051 with extra 8 bit ports). Subject : Re: Extend 64k Program Memory to 256K for 80C552 From : Scott May > In hardware configuration, because I want to uses this > microcontroller to access 256k bytes external program memory, > pin P1.0 & P1.1 of the microcontroller are connected to > A16 & A17 of a 256k bytes EEPROM. Now the external program > memory is divided to 4 bank. I don't have an answer as such, sorry, but there's a very good application note on this in the (dare I mention it here, on a Philips forum, damn, here goes) Dallas Semi High Speed micro data book. Find Application note 81. It's also available on their web site somewhere on http://www.dalsemi.com The information in it will work as well with any 8051 type. Subject : 8031 keyboard scanning via 8255 port C From : Greg.Goodhue@sv.sc.philips.com (Gregory Goodhue) reply to Buddy Mooneyhan: Hello, you said: >I noticed on some other schematics I have seen that the RD and PSEN pins >on the 8031 are attached to inputs of a gate,(1/4 of a 7404) and the >output of that gate tied to the RAM, 8255,etc RD pins. I don't have this >on my board. Am I correct in saying that when using MOVX type >instructions that the PSEN is used? Is the function of this gate to let >either RD or PSEN drive the 8255 RD pin low? If so, then this is a >problem of my own making, and one that I should be able to fix simply by >wiring in the gate. The reason that /RD and /PSEN are sometimes gated together is that this allows the 8051 to Write to RAMs (or some other readable/writable device) that it can also execute code from. The most typical example is in a system where there is some loader code in ROM/EPROM and this loads the RAM with the application code which it obtains from some other source (over a phone line, from a disk drive in a PC, etc.) MOVX reads or writes to DATA memory using the /RD and /WR signals. MOVC uses /PSEN to read code memory to be used as data. If your application uses MOVX to access the 8255 and does not need to execute from a RAM that it also reads and writes, then you should not need that extra gate. Subject : question about Burst Code Read of 80C51XA From : Greg.Goodhue@sv.sc.philips.com (Gregory Goodhue) Hello, you asked: > I have a question about 80C51XA operation. When is Burst Code Read > need and what is the policy of Burst Code Read? I appreciate in advance. Basically, the XA does burst mode code read whenever it can if it is executing from external code memory. It is easier to say when the XA does NOT use a burst fetch. 1) Crossing a 16-byte boundary. This is when the bottom four address bits increment to become all zeroes. An ALE is always required here because the latched portion of the address also changes. When the bus is configured as 8 bits, this means that the bottom four address lines (A3-A0) go low. When the bus is configured as 16 bits, the bottom three address lines (A3-A1) go low. In the 16-bit bus configuration, there is no A0 line. 2) A branch always causes an ALE cycle to precede the next fetch. Normally a branch will change the latched portion of the address. The XA does not have the means to detect when the branch wouldn't change the latched address and avoid the ALE cycle. The branch could be any branch instruction, including conditional branches where the branch is taken 3) When there is an interrupt or an exception, there are at least two ALE cycles needed (if ALL code is external). The first one in order to read in the vector location that corresponds to the interrupt or exception, the second to read the first byte or word of the handler code. A third ALE may sometimes be necessary to complete reading the entire first instruction of the handler code. This occurs when the instruction crosses a 16-byte boundary as in (1) above. Another point that may be of interest is that since the XA always tries to fetch code ahead of where it is executing (trying to fill up its pre-fetch queue), it may also abort code fetch cycles when a branch occurs. An aborted cycle is one that is not completed, it could have a short or missing /PSEN pulse. Because the XA is fetching ahead of execution, you can also see cases where an ALE cycle occurs for an address range that is never executed (because a branch occurs before the program flow reaches that address). Subject : Re: How to save ExRAM in From : Thomas Vegeby >I'm finishing the project, and I need simply to save 64 K external RAM in 8 >I2C Microchip 24LC65 SEEPROM. >Where can I find ASM source code of such procedure? XICOR has sample code for several different processors. http://www.xicor.com/xicor/menulink/link4.htm